Normally, a computer or digitally operable processing system includes a plurality of printed circuit boards ("PCBs") and the system is referred to as multi-board system. Typically, a multi-board system includes a master printed circuit board ("master board") on which a central processing unit (CPU) microprocessor, a memory unit, and other circuitry units generally associated with the system are typically arranged. Other PCBs in the system may include peripheral expansion boards that are coupled to the peripheral devices of the system for handling additional input/output operations of the system, and memory expansion boards that contain extra memory space for the system. These PCBs in the system are generally referred to as non-master boards. The non-master boards in the system are typically connected with the master board, and are controlled by the CPU to communicate with the units on the master board.
One prior multi-board system architecture is referred to in U.S. Pat. No. 4,905,182, issued on Feb. 27, 1990. This prior architecture includes a main circuit board ("mother board") on which slots are provided for expansion. When needed, expansion cards are placed into the slots, whereby forming the multi-board system. Each card plugged into the slots of the mother board may communicate with other cards and with the mother board through a bus system when selected by a board select signal, wherein the bus system may be a NUBUS bus system.
One disadvantage associated with the prior architecture is that a decoder and a comparator are required on each of the cards placed into the slots to receive its respective board select signal. In order to allow the cards to distinguish among themselves without jumper cables or switches, each slot is assigned a slot identification number. Each time an address appears on the bus, the decoder on the card decodes it which then is compared by the comparator of the card to the slot identification number of the slot into which the card is plugged. If the comparison results in a match, a chip select signal for the particular card is then locally generated by the comparator. The card is then selected and allowed to be addressed. The incorporation of the decoder and comparator requires additional hardware overhead for each expansion card and extra board area is required on each card to accommodate the additional hardware overhead.
Another prior multi-board system architecture is referred to in U. K. patent application GB 2,103,397A, published on Feb. 16, 1983. The prior architecture disclosed in FIG. 1 of the U. K. patent application includes a processing unit which can have access to different numbers of memory units over a common data bus. The processing unit can address the memory units with select signals over individual leads of an address bus. When a select signal appears on a particular lead that is coupled to one memory unit, the memory unit is selected.
One disadvantage associated with this prior architecture is that fixed or preassigned slot connections are required to couple each individual select signal to its respective unit. In order for a unit to be selected in the system, each unit needs to be coupled to a prearranged signal line to receive its select signal. Moreover, identification code is required for each slot to indicate if a unit is plugged in the slot. In addition, because of the fixed and preassigned slot configuration of the system, vacant slots are required in the system to anticipate future expansion.
Another prior multi-board system architecture which does not require any slots employs an UNIBUS bus system that serially connects the master board with other non-master boards (i.e., chained). Each expansion board includes a comparator and stores an identification code. When the master board decides to select a particular non-master board on the chain, it sends out a select signal corresponding to the identification code of that particular board. The first coupled board to the master board receives the select signal first. The board then compares the select signal against its identification code by an comparator. If they match, the board then accepts the signal as its select signal and blocks the signal from being transferred to the next connected board via the bus. If they do not match, the board then passes the select signal onto the next connected board until the select signal reaches the board that contains the matching identification code.
One disadvantage of this prior system is the logic delays which, in some cases, can be extremely long. For example, assuming the system includes n number of boards coupled serially to the master board via the UNIBUS bus and the logic delay of the select signal on each board is T, the total logic delay will be nT when the last board on the chain is selected.
Another disadvantage of this prior system is that no vacancy along the chain is allowed. If an intervening board is missing in the system, either a dummy board or a jumper is required to complete the chain and carry the select signal to the next connected board.